This invention concerns a magnetic spin polarisation device with a three-layered stack and memory using such a device.
It has applications in electronics and in particular and in particular for the manufacture of memory cells and MRAM (Magnetic Random Access Memory) type memories or direct access magnetic memories.
MRAM magnetic memories have enjoyed an increase in popularity with the development of magnetic tunnel junctions (MTJ) which exhibit high magneto-resistance at ambient temperatures. FIGS. 1A and 1B in the appendix show a schematic representation of the structure and function of such a junction.
The junction is indicated by item 2. It includes a stack having a layer of oxide sandwiched between two magnetic layers. The system operates like a spin valve, apart from the fact that the current flows perpendicular to the plane of the layers. One of the magnetic layers is described as xe2x80x9cfreexe2x80x9d because its magnetisation may be oriented by an external magnetic field (bi-directional arrow); the other is described as xe2x80x9canchoredxe2x80x9d because its magnetisation direction is anchored by an anti-ferromagnetic exchange layer (unidirectional arrow). When the magnetisation of the magnetic layers is anti-parallel, the resistance of the junction is high; when the magnetisation is parallel, the resistance is low. The relative variation of the resistance between these two states may be up to 40% by appropriate choice of materials.
Junction (2) is located between a switching transistor (4) and a current supply line (6). The current passing through the latter generates a magnetic field (7). A conductor (8), orthogonal to the current supply line (6) (i.e. in this case perpendicular to the plane of the figure) generates a second magnetic field (9) (located in the plane of the figure).
In xe2x80x9cwritexe2x80x9d mode (FIG. 1A), transistor (4) is blocked. Currents flow through the current supply line (6) and the conductor (8). Junction (2) is therefore subjected to two orthogonal magnetic fields. One is applied along the difficult magnetisation axis in the free layer, in order to reduce its reversal field, the other being applied along the easy magnetisation axis in order to generate a reversal of the magnetisation and write in the memory cells. In principle, only the memory cell located at the intersection of lines (6) and (8) is subject to reversal, since each magnetic field taken individually is insufficient to cause reversal of the magnetisation.
In xe2x80x9creadxe2x80x9d mode (FIG. 1B), the transistor is held in the saturated condition (i.e. the current flowing through it is at a maximum) by a positive current pulse in its base. The current flowing through line (6) only passes through the memory cell whose transistor is open. This current enables the resistance of the junction to be measured. By comparison with a reference memory cell, the state of the memory cell (xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d) may thus be determined.
Such a writing mechanism presents disadvantages particularly within a network of junctions.
1) As the reversal of the free layer magnetisation occurs under the effect of external fields, and since the reversal fields are statistically distributed, it is not impossible to accidentally reverse certain adjacent junctions simply by the effect of the magnetic field produced along the addressing line 6. As, for high density memories, the size of the memory cells is clearly sub-micronic, the number of addressing errors increases.
2) The reduction in size of memory cells results in an increase in the value of the individual reversal field; a larger current is therefore necessary to write in the memory cells, which tends to increase the electrical power consumption.
3) As writing necessitates two current lines at 90xc2x0, the constructional density is consequently limited by the presence of these lines.
4) The writing mode employed only enables writing into one memory cell at a time, if one wishes to minimise the danger of addressing errors.
Recently, other types of magnetic device have appeared, where the magnetic reversal is generated not by external magnetic fields but by electrons passing through the stack perpendicular to the plane of the layers. These devices are described in document U.S. Pat. No. 5,695,864. The mechanism employed is based on the transfer of magnetic moments between the electrons on the one hand, and the free layer magnetisation on the other hand. In such a system, the stack is formed of layers which are all electrically conducting, in order to limit the power dissipation. This results in several disadvantages
a) The resistance of the device is so low that a very high current must be injected in order to generate a voltage at the terminals comparable to that in conventional systems.
b) Such a current demands the use of a large size transistor, which limits the constructional density of the memory.
c) The amplitude of the variation in resistance obtained is very low (2-3%), which limits the output voltage.
d) For MRAM applications, the document referenced mentions three conductor levels and two voltage sources. A central conductor is intended to collect the polarised current used for reversal of the free layer. The device is therefore complex.
The present invention is therefore aimed at overcoming these disadvantages.
The invention aims to reduce the critical current density from which magnetisation reversal occurs in the free layer. The work and thinking of the Applicant have identified that this critical density is associated with the specific demagnetising field of the free layer. The invention therefore proposes a device in which this demagnetising field is very low or even zero. To achieve this, a three-layer stack is used (which will be referred to from now on as the xe2x80x9ctri-layer stackxe2x80x9d or simply xe2x80x9ctri-layerxe2x80x9d) formed of two magnetic layers separated by a non-magnetic conducting layer, the latter being thin enough for the coupling between the two magnetic layers to be strong enough for the magnetisation in these layers to be anti-parallel. Overall, such a system does not exhibit any (or only a slight) demagnetising field. The Applicant refers to such stacks as xe2x80x9csyntheticxe2x80x9d.
More precisely, the invention therefore concerns a magnetic device including:
a first magnetic layer known as the xe2x80x9canchoredxe2x80x9d layer, which exhibits a fixed magnetisation direction,
a second magnetic layer known as the xe2x80x9cfreexe2x80x9d layer, which exhibits a variable magnetisation direction,
an insulating or semi-conducting layer which separates the anchored and free layers,
means for passing a current of electrons through and perpendicular to the layers,
means for polarising the spin of those electrons,
characterized in that the free magnetic layer, at least, includes a first tri-layer stack having two anti-parallel magnetisation layers separated by a conducting non-magnetic layer.
In one design, the trapped layer itself consists of a tri-layer stack, this second stack being covered by an anti-ferromagnetic exchange layer which fixes the direction of magnetisation in the said second tri-layer stack.
In another design, the device includes a third tri-layer stack separated from the first by a conducting non-magnetic layer, this third tri-layer stack being mounted on a second anti-ferromagnetic exchange layer which fixes the magnetizations in this third tri-layer.
The material used for the magnetic layers in the first and/or second and/or third tri-layer stacks should preferably be chosen from the group consisting of Co, Fe, Ni and their alloys.
The non-magnetic conducting layer in the first and/or second and/or third tri-layer stacks should preferably be a metal chosen from the group consisting of Ru, Re, Cu, Cr, Pt, Ag.
The first and/or second anti-ferromagnetic layer may be a Mn-based alloy (e.g. FeMn, IrMn, PtMn, PtPdMn, RuRhMn).